分析并实现了一种用于产生多相时钟的延时锁定环电路。利用重复延时线和周期检测器,避免了复位信号和错误锁定的问题;采用信号路径对称的鉴相器,减小了抖动;使用电流舵技术,提高了电荷泵的开关速度。基于SMIC 0.18μm CMOS工艺,实现了一种产生32相时钟的延时锁定环,芯片核心尺寸为0.7mm×0.55mm,参考时钟频率范围为20~150MHz。仿真结果显示,在输入参考时钟频率为60MHz时,最长锁定时间为1.9μs,抖动为1ps,1.8V电源电压下的功耗为31.5mW。 A delay locked loop circuit for generating multiphase clock is analyzed and implemented. The use of repetitive delay lines and period detectors avoids the problem of reset signals and false locking; the use of a phase detector with a symmetrical signal path reduces jitter; and the use of a current steering technique improves the switching speed of the charge pump. Based on the SMIC 0.18μm CMOS process, a time-lag lock loop is achieved that produces a 32-phase clock with a chip core size of 0.7mm × 0.55mm and a reference clock frequency range of 20 to 150MHz. The simulation results show that the longest lock time is 1.9μs and the jitter is 1ps when the input reference clock frequency is 60MHz, and the power consumption is 31.5mW at 1.8V supply voltage.