提出一种基于确定性完备测试集的数字集成电路多加权集随机测试生成方法 .通过引入搜索与迭代算法 ,将完备测试集分成若干测试子集 ,每一子集对应一个权集 ,即产生该子集中测试矢量的被测电路各主输入端取‘1’值的概率组合 .该方法与文献 [2 - 3]的结果相比 ,在测试序列长度或硬件开销上获得了改善 ,对大规模集成电路的内建自测试尤为适用 This paper proposes a method for generating multi-weighted random test of digital integrated circuits based on a deterministic complete test set.Through the introduction of search and iterative algorithm, the complete test set is divided into a number of test subsets, each subset corresponds to a set of weights, that is, The probabilistic combination of the ’1’ values ​​at the main inputs of the circuit under test in the test vectors of subsets shows that the proposed method improves the test sequence length or hardware overhead compared with the results in [2 - 3] Integrated circuit self-test is particularly applicable