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为了减少数字锁相放大器中的数字信号处理模块在硬件实现时所占用的逻辑资源,采用多抽样率数字信号处理理论来降低被测信号的采样频率,设计了高性能的数字窄带低通滤波器。利用Hogenaur“剪除”理论的级联积分梳状(Cascade Integrator Comb,CIC)滤波器,在FPGA实现时不仅能够节省大量的硬件逻辑资源,而且提高了CIC滤波器的最小响应时间;利用内插二阶多项式滤波器(Interpolated Second Order Pofynomials,ISOP)使CIC滤波器通带衰减降低到0.4 dB左右。MATLAB与Modelsim联合仿真测试验证了设计的正确性与可行性。
In order to reduce the logic resources occupied by the digital signal processing module in the digital lock-in amplifier during the hardware implementation, the sampling frequency of the signal under test is reduced by adopting the multi-sample rate digital signal processing theory. A high-performance digital narrow-band low-pass filter . The Cascadic Integrator Comb (CIC) filter using Hogenaur’s “cut-off” theory not only saves a lot of hardware logic resources when implementing FPGA, but also increases the minimum response time of CIC filters. Interpolated Second Order Pofynomials (ISOP) reduce the passband attenuation of the CIC filter to about 0.4 dB. The joint simulation test between MATLAB and Modelsim validates the correctness and feasibility of the design.