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低密度奇偶校验码(LDPC)是目前最有效的差错控制手段之一,而其中准循环LDPC码(QC-LDPC)应用最为广泛。提出了一种通用的多码率QC-LDPC译码器设计方法,并在FPGA上完成了实现和测试。测试结果表明,该多码率译码器在资源占用不超过2种码率译码器资源之和的前提下能够有效支持至少3种码率;且工作时钟在110 MHZ时,固定迭代次数为16次,该译码器的吞吐率能保持在110 Mb/s以上。
Low density parity check code (LDPC) is one of the most effective error control methods currently available, and the quasi-cyclic LDPC code (QC-LDPC) is the most widely used. A general design method of multi-rate QC-LDPC decoder is proposed and implemented and tested on FPGA. The test results show that the multi-rate decoder can effectively support at least three kinds of code rates under the condition that resource occupancy does not exceed the sum of two kinds of rate decoder resources. When the working clock is at 110 MHZ, the number of fixed iterations is 16 times, the decoder throughput rate can be maintained at 110 Mb / s or more.