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本文讨论了用作高速开关和放大的平面型垂直DMOS FET的优化设计,出了能用于亚ns(毫微秒)开关的高压器件的设计考虑,并讨论了这种器件的版图设计和制造要求。然后评述了用于生产高速垂直DMOS FET的制造流程。工艺中的关键与特色是包括自对准多晶硅栅、全离子注入结、浮置的扩散保护环和金基金属化。用这种工艺作出的器件的重要电特性是漏—源击穿电压(BVDSS)>100V、共源截止频率(fco)=2GH_z。探讨了短沟DMOS器件的直流和交流特性模型。器件在测试电路中的性能表明,平面型垂直DMOS将是一种很好的高速、高压开关器件。
This article discusses the design optimization of a planar vertical DMOS FET for high-speed switching and amplification, designing considerations for high-voltage devices that can be used in sub-ns (nanosecond) switching, and discusses the layout design and fabrication of such devices Claim. Then reviewed the manufacturing process used to produce high-speed vertical DMOS FETs. Key features of the process include self-aligned polysilicon gates, all-ion implant junctions, floating diffusion guard rings, and gold-based metallization. The important electrical characteristics of devices fabricated using this process are drain-source breakdown voltage (BVDSS)> 100V and common source cut-off frequency (fco) = 2GH_z. The DC and AC characteristics of short-channel DMOS devices are discussed. The performance of the device in the test circuit shows that the planar vertical DMOS will be a good high speed, high voltage switching device.