提出了一种带氧化槽的双栅体硅LDMOS结构(DGT LDMOS)。在漂移区中引入一个氧化槽,在该槽上形成埋栅,同时形成一个槽栅。首先,双栅形成双导电沟道,减小了比导通电阻;其次,氧化槽折叠了漂移区,这不仅调制了电场的分布,而且提高了漂移区的优化浓度,有效提高了击穿电压,降低了比导通电阻。采用二维数值仿真软件MEDICI,对器件参数进行仿真和优化设计。结果表明,相对于普通体硅LDMOS(SG LDMOS),该结构的比导通电阻下降了56.9%,击穿电压提高了82.4%。在相同尺寸和击穿电压下,相对于单槽栅体硅LDMOS(SGT LDMOS),DGTLDMOS的比导通电阻下降了35.4%。 A double-gate silicon LDMOS structure with oxidation trench (DGT LDMOS) is proposed. An oxidation tank is introduced in the drift region, a buried gate is formed on the tank, and a trench gate is formed. First, the dual gate forms a double conductive channel, reducing the specific on-resistance. Second, the drift region is folded by the oxidation trough, which not only modulates the distribution of the electric field but also increases the optimized concentration of the drift region and effectively increases the breakdown voltage , Reducing the specific on-resistance. Using two-dimensional numerical simulation software MEDICI, the device parameters are simulated and optimized. The results show that the relative on-resistance of the structure is reduced by 56.9% and the breakdown voltage is increased by 82.4% compared with the general-purpose silicon LDMOS (SG LDMOS). At the same size and breakdown voltage, DGTLDMOS has a 35.4% reduction in specific on-resistance relative to a single trench gate silicon LDMOS (SGT LDMOS).