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基于断言的验证(Assertion Based Verification,ABV),是一种有价值的主流验证技术。断言特别适合于描述时序特性和因果特性。作为SystemVerilog的重要组成部分,SystemVerilogAssertion(SVA)提供了丰富的断言指令,能有效的提高验证测试工作的质量和效率。文章首先介绍了断言验证语言SystemVerilogAssertion,并针对ARM公司的AMBA总线中的AHB仲裁器模块的设计,给出了一种基于断言的验证方法,采用SVA对其进行验证测试。测试仿真的结果表明,本文给出的方法的有效性和正确性。
Assertion Based Verification (ABV) is a valuable mainstream verification technique. Assertions are particularly suitable for describing timing and causal characteristics. As an important part of SystemVerilog, SystemVerilogAssertion (SVA) provides a wealth of assertion instructions, which can effectively improve the quality and efficiency of verification testing. In this paper, the assertion verification language SystemVerilogAssertion is introduced at first. Aiming at the design of AHB arbiter module in ARM’s AMBA bus, an assertion-based verification method is presented. The verification is tested by SVA. The results of test simulation show that the method presented in this paper is valid and correct.