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本文讨论了高压NMOS集成器件中负阻击穿观象的机理。给出了发生负阻击穿的判定条件,建立了模型。 采用与目前国际上先进的主流工艺——n阱硅栅等平面CMOS工艺完全兼容的工艺流程,且无需增加任何工艺步骤,研制成一种新型的无负阻击穿的双栅型高压NMCS器件。在栅压为0～10V时,其漏源击穿电压大于300V,最大饱和电流大于0.3mA/单位宽长比(栅压为10V时),导通电阻为44kΩ·单位宽长比(栅压为10V时),具有广泛的应用价值。
This article discusses the mechanism of negative-resistance breakdown in high-voltage NMOS integrated devices. The judgment condition of negative resistance breakdown is given and the model is established. Adopting the process flow that is compatible with the current international advanced mainstream technology such as n-well silicon gate and other planar CMOS technology, a new type of double gate high voltage NMCS device with no negative resistance breakdown is developed without any additional process steps. When the gate voltage is 0-10V, the drain-source breakdown voltage is greater than 300V, the maximum saturation current is greater than 0.3mA / unit width-length ratio (gate voltage is 10V), and the on-resistance is 44kΩ. For 10V), has a wide range of applications.