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通过结合发光显微镜(EMMI)测试和poly-edge电容测试结构很好地控制了多晶硅刻蚀时间,避免了栅极氧化膜的早期失效.从栅极氧化膜击穿电压的测试结果可以看出,当刻蚀时间较短时,一个晶圆内几乎所有测试结构都呈现早期失效模式.通过延长刻蚀时间,早期失效数逐渐减少,最后可以完全消除早期失效,所有测试结构都为本征失效.为了分析多晶硅刻蚀时间和氧化膜失效模式的关系,对早期失效和本征失效样品进行了发光显微镜测试.Poly-edge电容结构的测试结果表明,过短的刻蚀时间导致了多晶硅在STI沟槽中的残留,硅化工艺后,这些多晶硅会使栅极和衬底短路,从而导致了栅极氧化膜的早期失效.通过延长刻蚀时间,可以有效地清除多晶硅的残留,从而保证栅极氧化膜的可靠性.
By combining the EMMI test and the poly-edge capacitance test structure, the polysilicon etching time is well controlled and the early failure of the gate oxide film is avoided.As can be seen from the test results of the breakdown voltage of the gate oxide film, When the etching time is short, almost all the test structures in one wafer exhibit the early failure mode. By prolonging the etching time, the number of early failures gradually decreases and finally the early failure can be completely eliminated. All the test structures are intrinsic failure. In order to analyze the relationship between the polysilicon etching time and the oxide film failure mode, the light-emitting microscopy tests on the early failure and intrinsic failure samples were carried out.The test results of the poly-edge capacitor structure show that too short etching time causes the polysilicon in the STI trench After the silicide process, these polycrystalline silicon short-circuit the gate and substrate, leading to the early failure of the gate oxide film. By prolonging the etching time, the polysilicon residue can be effectively removed to ensure the gate oxidation Film reliability.