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提出了一种基于新型源耦合逻辑或门的双模分频器和一种基于双D触发器的双模分频器。与传统的基于与门逻辑的双模分频器相比,基于新型源耦合逻辑的双模分频器减少了一级堆叠管,增加了采样开关管的过驱动电压,提高了工作速度。基于双D触发器的双模分频器比传统的基于4个D触发器的双模分频器节省近一半的晶体管,减小了芯片面积,降低了多模分频器的功耗。基于上述两种新型双模分频器架构,并引入分频比扩展技术,在0.18μm CMOS工艺下,实现了一种宽工作范围高速低功耗的多模分频器,分频范围为4～8192,工作频率范围0.8～2.7GHz,消耗电流1.25 mA。
A dual-mode divider based on a novel source-coupled logic OR gate and a dual-mode D-based divider are proposed. Compared with the traditional dual-mode divider based on AND logic, the dual-mode divider based on the new source-coupled logic reduces the first-level stacked tubes, increases the over-driving voltage of the sampling switch tube, and increases the working speed. Dual D-mode flip-flop based dual-mode dividers save nearly half the size of conventional dual-mode D-based dividers based on four D flip-flops, reducing chip area and power consumption in multi-mode dividers. Based on the above two new dual-mode divider architectures, and the introduction of frequency division ratio expansion technology, a 0.18μm CMOS technology to achieve a wide range of high-speed low-power multi-mode operation of the device, the frequency range of 4 ~ 8192, operating frequency range 0.8 ~ 2.7GHz, current consumption 1.25 mA.