基于ＳＲＡＭ 编程结构的门海型ＦＰＧＡ 连线上的时延较之ＡＳＩＣ来说比较大，连线延迟不可预测．在很多应用中必须对关键路径的时延加以定量限制（包括上限、下限和一组路径的时延差）．时延约束的实现需要布图算法来保证．一般时延驱动的布线算法只能定性地优化时延性能，不能满足定量要求．本文提出了高性能ＦＰＧＡ 最短路径布线算法，以它为主体的ＦＰＧＡ 布线器能全面地考虑各种时延约束，更好地利用布线资源，对其它无时延约束的线网也可进行时延优化，提高整个芯片的性能 Gate-based FPGA SRAM-based programming structure of the connection delay than the ASIC is relatively large, unpredictable connection delay. In many applications, the critical path latency must be quantitatively limited (including the upper limit, lower limit, and delay of a set of paths). The implementation of delay constraints needs a layout algorithm to ensure. General delay-driven routing algorithm can only qualitatively optimize the delay performance, can not meet the quantitative requirements. In this paper, the shortest path routing algorithm for high performance FPGA is proposed. The FPGA router based on it can fully consider various delay constraints and make better use of the routing resources, and can also delay other line networks with no delay constraint Optimize, improve the performance of the entire chip