Driven by continuous scaling of nanoscale semiconductor technologies,the past years have witnessed the progressive advancement of machine leing techniques and applications.Recently,dedicated machine leing accelerators,especially for neural networks,have attracted the research interests of computer architects and VLSI designers.State-of-the-art accelerators increase performance by deploying a huge amount of processing elements,however still face the issue of degraded resource utilization across hybrid and non-standard algorithmic kels.In this work,we exploit the properties of important neural network kels for both perception and control to propose a reconfigurable dataflow processor,which adjusts the patts of data flowing,functionalities of processing elements and on-chip storages according to network kels.In contrast to stateof-the-art fine-grained data flowing techniques,the proposed coarse-grained dataflow reconfiguration approach enables extensive sharing of computing and storage resources.Three hybrid networks for MobileNet,deep reinforcement leing and sequence classification are constructed and analyzed with customized instruction sets and toolchain.A test chip has been designed and fabricated under UMC 65 nm CMOS technology,with the measured power consumption of 7.51 mW under 100 MHz frequency on a die size of 1.8 × 1.8 mm2.