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论述了一种高速度低功耗的8位250 MHz采样速度的流水线型模数转换器(ADC)。在高速度采样下为了实现大的有效输入带宽,该模数转换器的前端采用了一个采样保持放大器(THA)。为了实现低功耗,每一级的运放功耗在设计过程中具体优化,并在流水线上逐级递减。在250 MHz采样速度下,测试结果表明,在1.2 V供电电压下,所有模块总功耗为60 mW。在19 MHz的输入频率下,SFDR达到60.1 dB,SNDR为46.6 dB,有效比特数7.45。有效输入带宽大于70 MHz。该ADC采用TSMC 0.13μm CMOS 1P6M工艺实现,芯片面积为800μm×700μm。
Discusses a high speed, low power, 8-bit 250 MHz sampling speed, pipelined analog-to-digital converter (ADC) The ADC uses a sample-and-hold amplifier (THA) on the front end for high effective input bandwidth at high-speed sampling. In order to achieve low power consumption, each stage of the op amp power consumption in the design process of specific optimization, and progressively decreasing in the pipeline. At 250 MHz sampling speed, the test results show that the total power consumption of all modules is 60 mW at 1.2 V supply voltage. At an input frequency of 19 MHz, the SFDR reaches 60.1 dB, the SNDR is 46.6 dB and the effective number of bits is 7.45. The effective input bandwidth is greater than 70 MHz. The ADC using TSMC 0.13μm CMOS 1P6M process to achieve the chip area of 800μm × 700μm.