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随着项目复杂程度的提高,系统级设计语言的整合趋势可以大大提高设计效率,并为处在电子设计自动化(EDA)行业中的设计企业带来益处。Sys-temVerilog 和 SystemC 这两种语言在设计流程中的共存,可以带来显著的实际利益和经济效果。
As project sophistication increases, the integration trend of system-level design languages can greatly improve design efficiency and benefit design firms in the electronic design automation (EDA) industry. The coexistence of the Sys-temVerilog and SystemC languages in the design process can bring significant tangible benefits and economic benefits.