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为了解决现有信息安全公钥签名算法存在的对大量模乘运算处理速度不快的问题,提出了一种高阶Booth编码的大数乘法器结构和二次编码的Booth 64线性变换式。二次编码既减少了部分积个数,也减少了高阶Booth编码预计算奇数倍的被乘数个数。基于此结构和编码,用Verilog代码设计了570×570b流水线乘法器。基于SMIC 0.18μm工艺,综合表明电路的关键路径延时为5.8 ns,芯片面积小于30mm2。可用于高性能的整数因子分解算法(RSA)2048 b、椭圆曲线算法(ECC)素数域512 b芯片的实现。
In order to solve the problem of large number of modular multiplication operations existing in the existing information security public key signature algorithm, a high-order Booth-coded large-scale multiplier structure and a quadratic-coded Booth 64 linear transform are proposed. The second encoding reduces the number of partial products and also reduces the number of multiplicands to be calculated by multiples of the higher order Booth encoding. Based on this structure and coding, a 570 × 570b pipeline multiplier is designed with Verilog code. Based on the SMIC 0.18μm process, the integrated circuit shows a critical path delay of 5.8 ns and a chip area of less than 30mm2. Can be used for high-performance integer factorization (RSA) 2048 b, elliptic curve algorithm (ECC) prime field 512 b chip implementation.