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用斜坡电压法(Voltage Ramp,V-ramp)评价了0·18μm双栅极CMOS工艺栅极氧化膜击穿电量(Charge toBreakdown,Qbd)和击穿电压(Voltage to Breakdown,Vbd).研究结果表明,低压器件(1·8V)的栅极氧化膜(薄氧)p型衬底MOS电容和N型衬底电容的击穿电量值相差较小,而高压器件(3·3V)栅极氧化膜(厚氧)p衬底MOS电容和n衬底MOS电容的击穿电量值相差较大,击穿电压测试值也发现与击穿电量相似的现象.其原因可以归结为由于光刻工艺对多晶硅/厚氧界面的损伤.该损伤使多晶硅/厚氧界面产生大量的界面态.从而造成了薄氧与厚氧n衬底和p衬底MOS电容击穿电量差的不同.从Weibull分布来看,击穿电压Weibull分布斜率比击穿电量.击穿电压的分布非常均匀,而且所有样品的失效模式都为本征失效,没有看到“尾巴”,说明工艺非常稳定.
The Voltage to Breakdown (Qbd) and Voltage to Breakdown (Vbd) of 0.18μm dual gate CMOS process were evaluated by Voltage Ramp (V-ramp) , The breakdown voltage of the gate oxide film (thin oxygen) of the low-voltage device (1.8V) differs slightly from the breakdown voltage of the N-type substrate capacitance, while the gate oxide film of the high voltage device (3.3V) (Thick oxygen) p substrate MOS capacitor and the n-substrate MOS capacitor breakdown power value difference between the breakdown voltage test values were also found to breakdown power similar phenomenon.The reason can be attributed to the lithography process of polysilicon / Oxygen interface.The damage caused a large number of interfacial states at the polycrystalline silicon / thick oxygen interface, resulting in the difference in the breakdown charge of the MOS capacitor between the thinner oxygen and the thicker n-substrate and the p-substrate. , Breakdown voltage Weibull distribution slope breakdown charge breakdown voltage distribution is very uniform, and all samples of the failure mode is an intrinsic failure, do not see the “tail”, indicating that the process is very stable.