An algorithm is presented for obtaining placements of cell|based very large scale integrated circuits, subject to timing constraints based on table|lookup model. A new timing delay model based on some delay tables of fabricators is first simplified and deduced; then it is formulated as a constrained programming problem using the new timing delay model. The approach combines the well|known quadratic placement with bottom|up clustering, as well as the slicing partitioning strategy, which has been tested on a set of sample circuits from industry and the results obtained show that it is very promising. An algorithm is presented for obtaining placements of cell | based very large scale integrated circuits, subject to timing constraints based on table | lookup model. A new timing delay model based on some delay tables of fabricators is first simplified and deduced; then it is formulated as a constrained programming problem using the new timing delay model. The approach combines the well | known quadratic placement with bottom | up clustering, as well as the slicing partitioning strategy, which has been tested on a set of sample circuits from industry and the results obtained show that it is very promising.