本文分析了参考文献[1]中所提出的设计方法中尚存在的两个问题并提出了一些修正办法:一,给出了主从J-K触发器的激励函数在二次时钟环以外应遵守的补充限制;二,给出了由已知的组合电路分析其输出电位的跳变边沿的情况以便检验其是否可以作为所要求的二次时钟信号的方法。同时,还讨论了与这两个问题有联系的某些冒险问题。本文可以作为对文献[1]的补充。 This paper analyzes two problems that exist in the design method proposed in [1] and proposes some corrections: First, it is given that the excitation function of master-slave JK flip-flop should be observed outside the secondary clock loop Supplementary limitations; Second, given by the known combinational circuit analysis of the output edge of the potential changes in order to test whether it can be used as the required secondary clock signal method. At the same time, some adventurous issues linked to these two issues were also discussed. This article can serve as a supplement to the literature [1].