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本文报导了两种36腿芯片-载体封装,它们能满足超高速砷化镓集成电路在3GHz时钟速率和100ps的上升下降时间要求。根据传输时延、抽头长度、串音干扰和电源等原则,对这种封装结构要求进行了分析,开发了两种具有内部接地平面、电源旁路电容器的封装和一种最大尺寸为1×1cm~2的封装;第一种封装途径基于多层共烧陶瓷技术,而第二种途径是利用把GaAsIC小片安装在象芯片-载体那样的一块硅IC表面的方法。就后一种情况而论,除了有较低的封装热阻外,这种硅-芯片还可提供屏蔽的传输线、电源调整、终端电阻器和衰减电阻器,以及能降低管壳的热阻等。
This article reports two 36-pin chip-carrier packages that meet the 3GHz clock rate and 100-ps rise-fall time requirements of very high speed GaAs integrated circuits. According to the principles of transmission delay, tap length, crosstalk interference and power supply, this kind of packaging structure is analyzed. Two kinds of packages with internal ground plane, power bypass capacitor and one kind of package whose maximum size is 1 × 1cm ~ 2 package; the first package based on multilayer co-fired ceramic technology, and the second approach is to use the GaAsIC chip mounted chip-like carrier like that of a silicon IC surface approach. In the latter case, in addition to lower package thermal resistance, the silicon-on-chip offers shielded transmission lines, power regulation, termination resistors and attenuation resistors, as well as reducing the thermal resistance of the package .