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在深入分析边沿触发器的功耗理论和时间特性的基础上,提出了新的设计方案。在SMIC 0.35μm CMOS标准工艺下,对该方案进行Spectre仿真,结果表明:新型结构比传统结构的延时下降48%左右,功耗下降26.22%。并且,在新设计方案中,双边沿触发器比单边沿触发器的延时下降36%,功耗下降19%。由此可见,新型边沿触发器,特别是新型双边沿触发器,不但能有效降低集成电路的功耗,而且对提高微系统的速度也有一定贡献。
Based on the in-depth analysis of the power dissipation theory and time characteristics of the edge trigger, a new design scheme is proposed. Specter simulation results show that the new structure reduces the delay by about 48% and the power consumption by 26.22% compared with the traditional structure under the SMIC 0.35μm CMOS standard process. And, in the new design, the bilateral edge flip-flop delay than the single-edge flip-flop 36%, 19% reduction in power consumption. Thus, the new edge-triggered devices, especially the new dual edge-triggered devices, not only can effectively reduce the power consumption of integrated circuits, but also to improve the speed of the micro-system also contribute.