A two stage scan architecture is proposed to do low power and low test application cost scan testing. The first stage includes multiple scan chains, where each scan chain is driven by a primary input. Each scan flip-flop in the multiple scan chains drives a group of scan flip-flops. The scan flip-flop in the multiple scan chain and the scan flip-flop driven by it are assigned the same values for all test vectors. Scan flip-flops in the multiple scan chains and those in the second stage use separate clock signals, but the design for testability technqiue needs only one clock. The proposed scan architecture localizes test power consumption to the multiple scan chains during test application. Test signals assigned to scan flip-flops in the multiple scan chains are applied to the scan flip-flops in the second stage after the test vector has been applied to the multiple scan chains. This technique can make test power consumption very small. A two stage scan architecture is proposed to do low power and low test application cost scan testing. Each scan flip-flop is driven by a primary input. Each scan flip-flop is driven by a primary input. group of scan flip-flops. The scan flip-flop in the multiple scan chain and the scan flip-flop driven by it are assigned the same values ​​for all test vectors. Scan flip-flops in the multiple scan chains and those in the second stage use separate clock signals, but the design for testability technqiue needs only one clock. The proposed scan architecture localizes test power consumption to the multiple scan chains during test application. Test signals assigned to scan flip-flops in the multiple scan chains are applied to the scan flip-flops in the second stage after the test vector has been applied to the multiple scan chains. This technique can make test power consumption very small.