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实现了一种8通道14位40MS/s流水线型A/D转换器。采用全差分开关电容结构的采样/保持电路,可以很好地抑制来自衬底的共模噪声,降低各种非线性因素引入的失真;利用“4+4+4×1.5+4”多级流水线结构的核心模数转换器单元,实现了转换器速度、精度、功耗以及版图面积的优化设计;基于电荷泵锁相环产生的1倍频和7倍频两组相位同步时钟信号,分别用于多级流水线采样保持和并行数据的并串转换;通过具有共模反馈的双电流源LVDS驱动器,实现了与外部560MB/s的高频数据接口。该电路采用0.18μm CMOS工艺,在时钟频率为40MHz,模拟输入频率为10MHz的条件下,实现了功耗≤1.2W,信噪比≥71dB,通道隔离度≥80dB。
An 8-channel 14-bit 40MS / s pipelined A / D converter is implemented. Using a fully differential switch capacitor structure of the sample / hold circuit, can be very good to suppress the common mode noise from the substrate, reducing the distortion introduced by a variety of nonlinear factors; the use of “4 +4 +4 × 1.5 +4” and more Level pipeline structure of the core ADC unit to achieve the converter speed, accuracy, power and layout area optimization design; based on the charge pump phase-locked loop generated 1 and 7 frequency multiplier two sets of phase synchronization clock signal, Respectively, for multi-stage pipelined sample-and-hold parallel data parallel conversion; with dual-current source LVDS driver with common-mode feedback to achieve an external 560MB / s high-frequency data interface. The circuit uses 0.18μm CMOS technology, the clock frequency of 40MHz, the analog input frequency of 10MHz under the conditions of power consumption ≤ 1.2W, signal to noise ratio ≥ 71dB, channel isolation ≥ 80dB.