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本文介绍一种采用冗余技术的5伏电源电压工作的256k×1位NMOS动态RAM。这种存器使用2.3微米设计规则,存贮单元设计为叠式位线结构,其行节距为6.5微米,读出放大器节距为18微米;硅化钽/多晶硅结构用作第二层多晶硅层,以减少行钱时间常数;存贮电容为60fF,而且采用HiC单元结构,这样使得存贮器具有很好的抗α粒子特性;管芯尺寸为4.66×11.65毫米,采用标准的0.3英寸(7.62毫米)厚的16腿双列直插式管壳封装。这种存贮器以256刷新周期工作,刷新时间为4毫秒;典型的RE/CE存取时间为105/65毫米微秒;工作功耗为250毫瓦,典型的维持功耗小于20毫瓦;这种存贮器与西方电气公司现有的5伏64k存贮器兼容。
This article presents a 256k × 1-bit NMOS dynamic RAM operating on a 5-V supply voltage using redundancy techniques. This register uses a 2.3 micron design rule and the memory cell is designed as a stacked bitline with a row pitch of 6.5 microns and a sense amplifier pitch of 18 microns. The tantalum silicide / polysilicon structure is used as a second polysilicon layer , To reduce the time constant for line transfer; storage capacitance of 60fF, and the use of HiC cell structure, so that the memory has good anti-α particle characteristics; die size 4.66 × 11.65 mm, using the standard 0.3 inches (7.62 Mm) thick 16-leg dual in-line package. This memory operates at 256 refresh cycles with a refresh time of 4 milliseconds, typical RE / CE access times of 105/65 milliseconds, operating power of 250 milliwatts and typical maintenance power of less than 20 milliwatts This memory is compatible with the existing 5-volt 64k memory at Western Electric.