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The design of low-power LVDS(low voltage differential signaling) transceiver ICs is presented.The LVDS transmitter integrates a common-mode feedback control on chip,while a specially designed pre-charge circuit is proposed to improve the speed of the circuit,making the highest data rate up to 622 Mb/s.For the LVDS receiver design, the performance degradation issues are solved when handling the large input common mode voltages of the conventional LVDS receivers.In addition,the LVDS receiver also supports the failsafe function.The transceiver chips were verified with the CSMC 0.5-μm CMOS process.The measured results showed that,for the LVDS transmitter with the pre-charge technique proposed,the maximum data rate is higher than 622 Mb/s.The power consumption is 6 mA with a 5-V power supply.The LVDS receiver can work properly with a larger input common mode voltage(0.1-2.4 V) but a differential input voltage as low as 100 mV The power consumption is only 1.2 mA with a 5-V supply at the highest data rate of 400 Mb/s.The chip set meets the TIA/EIA-644-A standards and shows its potential prospects in LVDS transmission systems.
The design of low-power LVDS (low voltage differential signaling) transceiver ICs is presented. The LVDS transmitter integrates a common-mode feedback control on chip, while a specifically designed pre-charge circuit is proposed to improve the speed of the circuit, making the highest data rate up to 622 Mb / s. For the LVDS receiver design, the performance degradation issues are solved when handling the large input common mode voltages of the conventional LVDS receivers. In addition, the LVDS receiver also supports the failsafe function. transceiver chips were verified with the CSMC 0.5-μm CMOS process. the measured results showed that for the LVDS transmitter with the pre-charge technique proposed, the maximum data rate is higher than 622 Mb / s. The power consumption is 6 mA with a 5-V power supply. The LVDS receiver can work properly with a larger input common mode voltage (0.1-2.4 V) but with a differential input voltage as low as 100 mV The power consumption is only 1.2 mA with a 5-V supply at the hi ghest data rate of 400 Mb / s. The chip set meets the TIA / EIA-644-A standards and shows its potential prospects in LVDS transmission systems.