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本文主要介绍了面向并行计算系统互连应用的复杂交换芯片(Switch ASIC)的芯片结构、设计权衡和物理实现。该交换芯片通过集成3路16x16交叉开关和特别垫垒处理单元,不仅可支持具有高吞吐量和低延迟的多层多功能包交换,而且还在其16个RX/TX端口间提供了先进的全局垫垒处理加速功能;以156.25MHz频率运行,拥有80Gbps端口交换和240Gbps内部包交换容量以及3.12Gbps的端口吞吐量。通过对一些芯片路径多模多角下时序的仔细调整以及对输出片上时钟网络的OCV优化,以微捷码的Blast工具为主达成了4种功能模式、3个PVT角点下芯片物理实现的完全时序收敛。目前,该芯片已通过0.18μm/6Metal CMOS技术完成投片,拥有约2000万个晶体管、17个不同的时钟域、48个RAM宏块、12.39mmx12.39mm芯片尺寸以及1053个引脚倒装芯片封装。
This article describes the chip architecture, design trade-offs, and physical implementation of a complex switch ASIC for parallel computing system interconnect applications. By integrating three 16x16 crossbar switches with a special pad processing unit, the switch not only supports multi-layer packet switching with high throughput and low latency, but also provides advanced Global pad processing Acceleration; Operates at 156.25MHz, with 80Gbps port switching and 240Gbps internal packet switching capacity and 3.12Gbps port throughput. By carefully adjusting the timing of multi-mode and multi-angle chips and optimizing the OCV of the output on-chip clock network, four functional modes have been achieved based on the Magma’s Blast tool. The complete physical implementation of the chip at three PVT corners Timing closure. Currently, the chip has been completed by 0.18μm / 6Metal CMOS technology to cast, with about 20 million transistors, 17 different clock domains, 48 RAM macroblocks, 12.39mmx12.39mm chip size and 1053 pin flip chip Package.