【摘 要】
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Based on the flexible quadtree partition structure of coding tree units ( CTUs) , the deblocking filter ( DBF) in high efficiency video coding ( HEVC) consumes a lot of resources when implemen-ted by hardware. It is difficult to achieve flexible switching
【机 构】
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School of Computing Science&Technology,Xi’an University of Posts and Telecommunications,Xi’an 710121
论文部分内容阅读
Based on the flexible quadtree partition structure of coding tree units ( CTUs) , the deblocking filter ( DBF) in high efficiency video coding ( HEVC) consumes a lot of resources when implemen-ted by hardware. It is difficult to achieve flexible switching between different sizes of coding blocks. Aiming at this problem, a reconfigurable implementation of DBF is proposed. Based on the dynamic programmable reconfigurable video array processor ( DPRAP ) with context switch reconfiguration mechanism, the runtime flexible switching of two coding block sizes is realized. The experimental results show that the highest work-frequency reaches 151. 4 MHz. Compared with the dedicated hardware architecture scheme, the resource consumption can be reduced by 28. 1% while realizing the dynamic switching between algorithms of two coding block sizes. Compared with the results of HM16. 0, by using a complete I-frame for testing, the average peak signal-to-noise ratio (PSNR) of the reconfigurable implementation proposed in this paper has increased by 3. 0508 dB, the coding quality has improved to a certain extent.
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