【摘 要】
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This paper reports a successive approx-imation register(SAR)analog-to-digital converters(ADCs)with the 2nd-order and optimized noise shaping(NS)scheme.Based on the feed-forward structure,both noise transfer function(NTF)zero and pole optimization have bee
【机 构】
:
School of Microelectronics,Xidian University,Xi’an 710071,China
论文部分内容阅读
This paper reports a successive approx-imation register(SAR)analog-to-digital converters(ADCs)with the 2nd-order and optimized noise shaping(NS)scheme.Based on the feed-forward structure,both noise transfer function(NTF)zero and pole optimization have been achieved simultaneously utilizing a cascaded IIR-FIR(infinite impulse response and finite impulse re-sponse)filter.The analysis shows that the proposed struc-ture provides a better NS efficiency than prior arts.The efficiency of the proposed NS scheme and the ADC per-formance are verified by simulation achieving a 14.2 ef-fective number of bits with an 8-bit SAR ADC architec-ture at an over sampling rate of 8 sampled at 100 MS/s.Taking advantage of the NTF zero-pole optimization,a low resolution SAR ADC is allowed under the same quantization noise budget in this structure.
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