：针对层次式设计的集成电路版图，提出一种分级式的版图设计规则检查算法．通过提取和使用单元图形抽象，结合浮出重叠区覆盖下的子单元图形的方法，确定了各单元在任意布局下的设计规则检查（ＤＲＣ）运算图形集，可以处理各种重叠情况．分级式ＤＲＣ分别对每个单元的ＤＲＣ图形集作一次检查，与打散式相比，大大减少了处理重复单元多的大规模、超大规模集成电路版图的工作量，从而缩短了检查时间，降低了内存需求，且更便于设计者修改错误 : In view of the hierarchical layout of the integrated circuit, a hierarchical layout design rule checking algorithm is proposed. By extracting and using unit graphic abstraction and combining with the subunit graphic covering the overlapped area, the design rule checking (DRC) operation graphic set of each unit under any layout is determined, and various overlapping situations can be handled. The hierarchical DRC examines the DRC graphset of each cell separately. Compared with the scattergap, the DRC drastically reduces the workload of processing large-scale and very large-scale integrated circuit layouts with many repetitive cells, thereby shortening the inspection time and reducing Memory requirements, and easier for designers to change the error