We propose a class of Rate-compatible(RC) Low-density parity-check(LDPC) codes with a very wide range of code rates. To widen the range of rates, we have developed an optimal transmission scheme to push the upper bound of code rates to 0.96. Characterized by a parity check matrix in a dual-diagonal form, the proposed RC LDPC code can be encoded in linear time. Constructed from shifted identity sub-matrices, the proposed codes are particularly well-suited for the high-speed implementation of parallel encoders. Furthermore, the encoder can be implemented efficiently with several left circular shifters and XOR gates. To maximize the encoding speed, we have proposed a q-parallel encoder architecture, where q is the size of each sub-matrix. The implementation results into Field programmable gate array(FPGA) devices indicate that a72-parallel encoder for the proposed RC LDPC code with a code rate from 0.5 to 0.96 is capable of reaching a speed of 42 Gigabits per second(Gbps) using a clock frequency of 300 MHz. We propose a class of Rate-compatible (RC) Low-density parity-check (LDPC) codes with a very wide range of code rates. We have developed an optimal transmission scheme to push the upper bound of code rates to 0.96. Characterized by a parity check matrix in a dual-diagonal form, the proposed RC LDPC code can be encoded in linear time. Constructed from shifted identity sub-matrices, the proposed codes are particularly well-suited for the high- speed implementation of parallel encoders. Furthermore, the encoder can be highly efficient with several left circular shifters and XOR gates. The implementation results into field programmable gate array (FPGA) devices indicate that a72-parallel encoder for the proposed RC LDPC code with a code rate from 0.5 to 0.96 is capable of reaching a speed of 42 Gigabits per second (Gbps) using a clock fr equency of 300 MHz.