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CMOS集成电路已经有10年以上的工艺历史,可以说它的成功在于CMOS的低功耗性。由于PMOS和NMOS的共存,降低了集成度并增加了工艺的复杂性,从而提高了制造成本,这同NMOS LSI相比,可认为CMOS在VLSI化中有决定性的不利条件。终而,尽管NMOSLSI采用各种电路办法,譬如动态型电路和内部时(?)同步型电路等,但在功耗和噪声容限等方面正在接近于极限,而且随着电路的改良,工艺也变得非常复什了。而CMOS电路一方面保持了低功耗,高噪声容限,宽的工作电压和宽的工作温度区这样的CMOS本质特点,另一方面也正在迅速不断地提高集成度。
CMOS integrated circuits have more than 10 years of process history, it can be said that its success lies in CMOS low-power. The coexistence of PMOS and NMOS reduces integration and increases the complexity of the process, thereby increasing the manufacturing cost, which is considered to be a decisive disadvantage of VLSI in comparison with the NMOS LSI. In the end, although NMOSLSI uses various circuit approaches, such as dynamic and internal (?) Synchronous circuits, it is approaching its limits in terms of power consumption and noise margin, and as circuits are being improved, It is very complicated. The CMOS circuit, on the other hand, maintains the CMOS nature of low power consumption, high noise margin, wide operating voltage and wide operating temperature range. On the other hand, the CMOS circuit is rapidly increasing the integration level.