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日本电电公社武藏野电气通信研究所试制成功了15级的E/D结构的GaAsFET环形振荡器,每门延迟时间为19.6ps,功耗为8.6mW/门,这是室温工作的GaAs IC的最高值。该FET使用三层抗蚀层(抗蚀剂-SiO_2-抗蚀剂)和剥离方法,并利用抗蚀剂的钻蚀,将有效栅长缩短到0.5μm,同时降低源电阻。用离子注入方法,形成n~+漏区和源区。n~+层和肖特基栅金属的间距很短,小于0.3μm,这个距离可用最下层的抗蚀剂的钻蚀量来控制,如果该间距大于0.3μm,则源电阻就要增加,如果为零,栅耐压就要下降。器件采用了直拉法生长的掺铬
Japan Electric Power Corporation Musashino Electric Institute of communications trial success 15 grade E / D structure GaAsFET ring oscillator, each delay time of 19.6ps, power consumption of 8.6mW / gate, which is working at room temperature GaAs IC The highest value. The FET uses a three-layer resist (resist-SiO2-resist) and lift-off method and utilizes resist etch-down to shorten the effective gate length to 0.5 μm while reducing the source resistance. Using ion implantation, n ~ + drain and source regions are formed. The distance between the n ~ + layer and the Schottky barrier metal is very short, less than 0.3 μm. This distance can be controlled by the amount of undercut resist etch. If the spacing is greater than 0.3 μm, the source resistance is increased. If To zero, gate voltage will drop. The device uses a Czochralski method for growth