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The performance of an integrated packet voice/data multiplexer using a stop-and-wait (SW) automatic repeat request (ARQ) protocol is discussed. We assume that the input for the data traffic is exponentially distributed in increments via the Poisson process, with each data packet transmitted within an individual slot time. Another assumption is that there is only a single voice signal, which has a higher priority over the data packet, and whose traffic is given via an on-off Markov process. Whenever the voice signal is active, the output link is used and will be blocked for the data packet. We introduce the concept of buffer occupancy to simplify the analysis, and discover that data multiplexers using the SW ARQ protocol exhibit a behavior of queueing delay and buffering when the interruption signal is given via a Markov process. Simulation results verify the validity of the analytical results.