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用简单的鉴频鉴相器结构实现了一个快锁定低抖动的锁相环.鉴频鉴相器仅仅由两个异或门组成,它可以同时获得低抖动和快锁定的性能.锁相环中的电压控制振荡器由四级环形振荡器来实现,每级单元电路工作在相同的频率,并提供45°的相移.芯片用0.18μmCMOS工艺来实现.PLL输出的中心频率为5GHz,在偏离中心频率500kHz处,测量的相位噪声为-102.6dBc/Hz.锁相环的捕获范围为280MHz,RMS抖动为2.06ps.电源电压为1.8V时,功耗仅为21.6mW(不包括输出缓冲).
A simple phase-locked loop with fast-lock, low-jitter, is realized with a simple phase-frequency detector structure. The phase-frequency detector consists of only two XOR gates that achieve both low jitter and fast-lock performance. The voltage controlled oscillator is implemented by a four-stage ring oscillator, and each stage of the unit operates at the same frequency and provides a 45 ° phase shift. The chip is implemented with a 0.18μm CMOS process. The center frequency of the PLL output is 5GHz, Measured phase noise is -102.6dBc / Hz at 500kHz from the center frequency. The capture range of the phase-locked loop is 280MHz and the RMS jitter is 2.06ps. The power consumption is only 21.6mW at a supply voltage of 1.8V (not including the output buffer ).