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设计了一个5位330 MS/s的异步数字斜坡模数转换器(ADC)。采用中芯国际55nm工艺和Cadence Virtuoso软件,对电路进行设计和仿真。供电电源为1.2V,改进后的延迟单元将延迟时间缩短到50ps。另外,该电路中的比较器采用自动关闭方式,节省了功耗。输入电压峰峰值为0.4V时,仿真得到信噪失真比(SNDR)为28.19dB,有效位(ENOB)为4.39位,无杂散噪声动态范围(SFDR)为35.87dB,信噪比(SNR)为31.47dB。
A 5-bit, 330 MS / s asynchronous digital ramp analog-to-digital converter (ADC) is designed. Design and simulate the circuit using SMIC’s 55nm process and Cadence Virtuoso software. The power supply is 1.2V, the improved delay unit shortens the delay time to 50ps. In addition, the comparators in this circuit are automatically shut down to save power. When the input voltage is 0.4V, the SNDR is 28.19dB, the ENOB is 4.39, the spurious noise SFDR is 35.87dB, the signal to noise ratio (SNR) 31.47dB.