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针对高的相位噪声指标要求,对取样锁相介质振荡器进行了研究。通过相位噪声分析,明晰了采用介质振荡器与取样锁相技术降低相位噪声的机理,并分别对介质振荡器与锁相环路进行了设计。设计中,应用HFSS与ADS对介质振荡器进行了联合仿真,体现了计算机辅助设计的优势。最终研制出17 GHz锁相介质振荡器,测试结果为:输出功率13.1 dBm;杂波抑制>70 dB;谐波抑制>25 dB;相位噪声为-105 dBc/Hz@1 kHz,-106 dBc/Hz@10 kHz,-111 dBc/Hz@100 kHz,-129 dBc/Hz@1 MHz。
Aiming at the requirement of high phase noise index, the sample-locked-phase dielectric oscillator is studied. Through the phase noise analysis, the mechanism of reducing the phase noise by the dielectric oscillator and the sampling phase-locked technique is clarified, and the dielectric oscillator and the phase-locked loop are respectively designed. Design, the application of HFSS and ADS on the media oscillator co-simulation, embodies the advantages of computer-aided design. Finally, a 17 GHz phase-locked dielectric resonator was developed. The test results were as follows: output power 13.1 dBm; clutter suppression> 70 dB; harmonic rejection> 25 dB; phase noise -105 dBc / Hz @ 1 kHz -106 dBc / Hz @ 10 kHz, -111 dBc / Hz @ 100 kHz, -129 dBc / Hz @ 1 MHz.