传统上,数字逻辑的静态功耗不会很高,然而在非常小的工艺节点上,这种情况发生了变化。随着工艺尺寸的降低,数字逻辑的泄漏电流成为FPGA面临的主要挑战。虽然迈向65nm工艺实现了摩尔定律预言的密度和性能优势,但是性能的提高也会显著增加功耗,有可能出现无法承受的高功耗。 Traditionally, the static power consumption of digital logic has not been high, but this has changed on very small process nodes. As process dimensions decrease, digital logic leakage current becomes a major challenge for FPGAs. While moving toward a 65nm process achieves the density and performance advantages predicted by Moore’s Law, increased performance can significantly increase power consumption and potentially unacceptably high power consumption.