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利用现场可编程门阵列(FPGA,Field Programmable Gate Array)实现了一种基于深空通信的级联码结构。该级联码包括内码和外码,内码是基于全并行的软判决Viterbi译码器结构,用来纠正随机错误,结合帧同步技术完成解交织,然后进行外码里德-所罗门码(RS codes,Reed-solomon codes)译码,纠正突发错误,实现级联码译码。通过实际硬件测试,在满足系统误码率要求的前提下,使用该级联码译码器能够降低发射功率或减少天线尺寸,对降低系统成本及提高系统性能具有非常重要的作用。
A field-programmable gate array (FPGA) is used to realize a concatenated code structure based on deep space communication. The concatenated code includes an inner code and an outer code. The inner code is based on an all-parallel soft decision Viterbi decoder structure, which is used to correct random errors. The de-interleaving is performed according to the frame synchronization technique, and then the outer code Reed-Solomon code RS codes, Reed-solomon codes) decoding, correct bursts of errors, cascading code decoding. Through the actual hardware test, under the premise of meeting the system error rate requirement, using the concatenated code decoder can reduce the transmit power or reduce the antenna size, which plays an important role in reducing the system cost and improving the system performance.