论文部分内容阅读
微处理器内部嵌入的定时器数量有限,虽然有外扩3个16位定时器的芯片,但难以满足需求。因此应用FPGA研制具有7个16位定时器IP核,设计命令字,设置命令字可以组成3个32位定时器,4个基准定时单位的选择,自动装载定时参数,能够与微处理器接口,提高微处理器的定时操作处理效率。阐述定时器系统的结构和各组成模块的工作原理,定时器定时计数的流程图。以定时器IP核与89C51单片机接口为例,说明定时器IP核的初始化编程步骤,定时运行过程中的应用方法。
The number of timers embedded in the microprocessor is limited, although there are three 16-bit timers that expand outside the chip, but difficult to meet the demand. Therefore, the application of FPGA development with seven 16-bit timer IP core, the design of the command word, set the command word can be composed of three 32-bit timers, four reference timing unit selection, automatic loading timing parameters, to interface with the microprocessor, Improve the microprocessor’s timing operation processing efficiency. Describe the structure of the timer system and the working principle of the various modules, timer timer count flow chart. Taking timer IP core and 89C51 singlechip as examples, it shows the initialization procedure of timer IP core and the application method in regular operation.