In this paper we describe a full-integrated circuit containing all building blocks of a completed PLL-based synuhesizer except for low pass filter(LPF).The frequency synthesizer is designed for a frequency hopping (FH) transceiver operating up to 1.5 GHz as a local oscillator. The architecture of Voltage Controlled Oscillator (VCO) is optimized to get better performance, and a phase noise of -111.85-dBc/Hz @ 1 MHz and a tuning range of 250 MHz are gained at a centre frequency of 1.35 GHz.A novel Dual-Modulus Prescaler(DMP) is designed to achieve a very low jitter and a lower power.The settling time of PLL is 80 μs while the reference frequency is 400 KHz. This monolithic frequency synthesizer is to integrate all main building blocks of PLL except for the low pass filter,with a maximum VCO output frequency of 1.5 GHz,and is fabricated with a 0.18 μm mixed signal CMOS process. Low power dissipation, low phase noise, large tuning range and fast settling time are gained in this design. In this paper we describe a full-integrated circuit containing all building blocks of a completed PLL-based synuhesizer except for low pass filter (LPF). The frequency synthesizer is designed for a frequency hopping (FH) transceiver operating up to 1.5 GHz as a local oscillator. The architecture of Voltage Controlled Oscillator (VCO) is optimized to get better performance, and a phase noise of -111.85-dBc / Hz @ 1 MHz and a tuning range of 250 MHz are gained at a center frequency of 1.35 GHz. A novel Dual-Modulus Prescaler (DMP) is designed to achieve a very low jitter and a lower power. The settling time of PLL is 80 μs while the reference frequency is 400 KHz. This monolithic frequency synthesizer is to integrate all main building blocks of PLL except for the low pass filter, with a maximum VCO output frequency of 1.5 GHz, and is fabricated with a 0.18 μm mixed signal CMOS process. Low power dissipation, low phase noise, large tuning range and fast settling time are gained in this design .