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半导体工艺迈人纳米阶段,IC光罩和设计成本急速提高,半导体厂商在进行设计时承受的风险也愈来愈高,半导体厂如Intel、Transmeta、Rambus 皆曾传出收回瑕疵芯片的新闻,错失产品上市时间,损失甚钜。Versity市场行销暨业务开发副总裁Steve Glaser表示,IC设计纠错的环节包括Logic、Signal Noise、Critical Path、Clocking、Pace Condition,其中有74％的比例是来自Logic Error,Versity的EDA产品就是着重于系统层级的验证,解决Logic Error的问题。
Semiconductors, nano-stage technology, IC mask and the rapid increase in design costs, semiconductor manufacturers in the design of the risk is also getting higher and higher, semiconductor companies such as Intel, Transmeta, Rambus have heard the news of the recovery of defective chips, missing Product time to market, huge loss. Steve Glaser, vice president of marketing and business development at Versity, said IC design errors include Logic, Signal Noise, Critical Path, Clocking, Pace Condition, 74% of which are from Logic Error and Versity’s EDA product focuses on System-level verification to solve Logic Error problems.