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文章对深亚微米条件下的SRAM存储单元的静态噪声容限进行了详细的理论分析。并在此基础上分析考虑了各种因素对静态噪声容限的影响,并利用Hspice软件进行了仿真。仿真结果显示,理论分析的结果与实际相吻合。
The paper makes a detailed theoretical analysis of the static noise margin of SRAM cells in deep submicron. On this basis, the influence of various factors on the static noise margin is analyzed and analyzed, and the simulation is carried out by using Hspice software. Simulation results show that the theoretical analysis is consistent with the actual results.