引脚数量多的高速集成电路的设计成功,需要封装工程师和芯片设计师在这项工程中自始至终密切合作,进行协同设计。随着高速数据接入、传输和存储从高端计算设备和远程SONET(同步光纤网)设备转向便携式计算设备和以太网LAN(局域网)应用的日益广泛。半导体器件在满足日益苛刻的性能要求的同时必须变得更加经济实惠。目前,能以通常高 The successful design of high-speed integrated circuits with a large number of pins requires packaging engineers and chip designers to work closely together throughout the project for collaborative design. As high-speed data access, transport and storage become more widespread from high-end computing devices and remote SONET (Synchronous Optical Network) devices to portable computing devices and Ethernet LAN (local area network) applications. Semiconductor devices must become more affordable while meeting increasingly demanding performance requirements. Currently, it can be usually high