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采用 Ga/AsCl_3/H_2汽相外延在掺杂半绝缘衬底上生长 FET 的缓冲层。用霍耳、光霍尔、阴极荧光以及新的深能级瞬态电流法(DLTS)研究了缓冲层的双层结构。此双层结构由上层的高纯 n~-层(10~(13)≤n≤10~(15)cm~(-3);70000≤μ≤150000cm~2V~(-1)s~(-1))和下边的高阻补偿区两个部分组成。采用电解质-GaAs 接触,观察到 p 型界面。迁移率分布与界面和衬底的碳和铬(可能还有铁)的外扩散有关。并由此提出补偿模型。
The buffer layer of FET is grown on the doped semi-insulating substrate by Ga / AsCl_3 / H_2 vapor phase epitaxy. The double-layer structure of the buffer layer was investigated by Hall, Hall of Light, cathodic fluorescence and a new deep level transient current method (DLTS). The double-layer structure consists of a high-purity n ~ - layer (10 ~ (13) ≤n≤10 ~ (15) cm ~ (-3)), 70000≤μ≤150000cm ~ 2V ~ 1)) and below the high impedance compensation zone composed of two parts. Using electrolyte-GaAs contacts, a p-type interface was observed. The mobility distribution is related to the out-diffusion of carbon and chromium (and possibly iron) in the interface and the substrate. And then proposed compensation model.