论文部分内容阅读
介绍了一种新的高速集成逻辑电路。它不同于常用集成逻辑电路那样基于一种基本单元门电路,而是由几种基本单元组合而成所需的逻辑系统,因而并不要求每种基本单元都有阈值特性。其主要基本单元就是一种高速线性“与或”门,工艺很简单。用较粗尺寸工艺试作的四位全加器进位链样品,实测速度为每级进位上升边延迟1ns,下降边延迟更小。每门最大功耗12.5mw。文中还与几种原有的集成辑逻电路进行了分析比较。
A new high-speed integrated logic circuit is introduced. It is different from the common integrated logic circuit based on a basic cell gate, but by the combination of several basic elements of the required logic system, so do not require each of the basic unit has threshold characteristics. Its main basic unit is a high-speed linear “and or” door, the process is very simple. The four-bit full adder carry chain sample, which was made with the coarser size process, was measured with a delay of 1 ns for each stage of carry rising and a smaller delay for falling. Each door maximum power consumption 12.5mw. The article also with several original integrated circuit logic analysis and comparison.