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为实现一种能够自主完成浮点数加/减、乘、除运算功能的浮点数算术运算执行控制器,提出了一种基于采用FPGA的并行操作设计硬连接的浮点算术运算控制电路及其时序控制方法,该控制器能够自动选择运算器,调整内部时序脉冲的时钟周期,自主完成操作数的配置并进行浮点数加/减、乘、法运算的功能,运算结果读到系统数据总线;论述了该控制器的电路构成和基本原理,分析操作数配置与运算器的选择,及内部时序脉冲作用下的执行过程,应用Verilog HDL语言实现相关硬件的构建和连接;通过仿真综合测试可知,该控制器的最高频率可达132.426M,从输入端口到输出端口的延时数据为:最小延时是5.367ns,最大延时是18.347ns,耗用的IO输入输出端口占总资源的31.45%;并能够自动选择运算器,自主完成相应的算术运算。
In order to realize a floating-point arithmetic implementation controller capable of completing floating-point addition, subtraction, multiplication and division, a floating-point arithmetic control circuit based on parallel operation of FPGA and its timing Control method, the controller can automatically select the arithmetic unit, adjust the clock cycle of the internal timing pulse, independently complete the configuration of the operands and perform the functions of adding, subtracting, multiplying, and floating-point numbers, and reading the result to the system data bus; The circuit structure and basic principle of the controller are analyzed, the selection of operand configuration and operation unit is analyzed, and the execution process under the action of internal timing pulse is implemented. Verilog HDL language is used to realize the construction and connection of related hardware. Through the simulation comprehensive test, The maximum frequency of the controller is 132.426M. The delay data from the input port to the output port is: the minimum delay is 5.367ns, the maximum delay is 18.347ns, and the IO input and output ports consume 31.45% of the total resources. And can automatically select the arithmetic unit, independent of the corresponding arithmetic operation.