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如果在P—n结的分界面上有大的漏电流,以致不能有效地绝缘两个区域,那末,导电类型与衬底相反的外延层的电学性质的测量就出现了严重的问题。在测量时,为了不破坏这种结构,一种改进的霍耳技术发展起来了。改进的霍耳技术对外延层和衬底的霍耳系数同时进行测量,也测量了界面的阻抗,模型化并考虑了两个区域之间的相互作用。这项技术能够用来证实:对于高阻衬底的干扰影响可以忽略的那些情况就可以在外延层上进行常规测量。如果模型的假设条件是满足的,这种方法原则上能够用来分别测量各层的电阻率和霍耳系数。本文讨论了如何使用这项技术以及该技术在下列两种衬底上生长的薄n型硅外延层上的应用:1)在P—n结分界面上有大漏电量的掺锢硅导电衬底。2)对测量外延层霍耳系数的影响可以忽略不计的高电阻率硅衬底。
If there is a large leakage current at the interface of the P-n junction so that the two regions can not be effectively insulated, the measurement of the electrical properties of the epitaxial layer of the conductivity type opposite to the substrate presents a serious problem. In the measurement, in order not to damage this structure, an improved Hall technology developed. The improved Hall-effect technique simultaneously measures the Hall coefficient of the epitaxial layer and the substrate, as well as the impedance of the interface, and models and considers the interaction between the two regions. This technique can be used to confirm that conventional measurements on the epitaxial layer can be made in those cases where the interference effects of the high-resistance substrate are negligible. If the assumptions of the model are fulfilled, this method can in principle be used to measure the resistivity and the Hall coefficient of each layer separately. This article discusses how to use this technique and its application to thin n-type epitaxial layers grown on the following two substrates: 1) Silicon-filled conductive liner with large leakage at the P-n junction interface bottom. 2) High-resistivity silicon substrate with negligible impact on Hall coefficient of epitaxial layers.