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基于预放大-锁存理论,提出了一种带1级预放大器的高速CMOS锁存比较器电路拓扑 结构;阐述了其传输延迟时间、回馈噪声和输入失调电压的改进方法。采用典型的0.35μm／3.3 V 硅CMOS工艺模型,通过Cadence进行模拟验证,得到其传输延迟时间380 ps,失调电压6.8 mV, 回馈噪声对输入信号产生的毛刺峰峰值500μV,功耗612μW。该电路的失调电压和回馈噪声与带 两级(或两级以上)CMOS预放大锁存比较器的指标相近,且明显优于锁存比较器。其功耗和传输 延迟时间介于两种比较器之间。该电路可用于高速A／D转换器模块与IP核设计。
Based on the theory of preamplifier - latch, a high speed CMOS latch comparator topology with a preamplifier is presented. An improved method for the propagation delay, feedback noise and input offset voltage is presented. The typical 0.35μm / 3.3V silicon CMOS process model is verified by Cadence. The transfer delay time is 380 ps and the offset voltage is 6.8 mV. The feedback noise produces a peak spike value of 500μV and a power consumption of 612μW for the input signal. The circuit’s offset voltage and feedback noise are comparable to those of the CMOS pre-latched comparator with two stages (or more) and are significantly better than the latch comparator. Its power consumption and transmission delay time between the two comparators. This circuit can be used for high-speed A / D converter module and IP core design.