设计了一种应用于10位80 MS/s流水线A/D转换器的可调节多相时钟产生电路。该电路采用一种电流镜结构,通过调节可变电阻的阻值来实现对单位延迟时间的精确控制。芯片采用IBM 0.13μm CMOS工艺实现,电源电压为2.5 V。在各种条件下仿真所得的最大延迟时间偏差为4%,时钟电路功耗为0.68 mW。仿真结果表明,该时钟产生电路适用于高速流水线A/D转换器。 An adjustable multi-phase clock generator circuit is designed for 10-bit 80 MS / s pipelined A / D converter. The circuit uses a current mirror structure, by adjusting the resistance of variable resistors to achieve the precise control of the unit delay time. The chip is implemented in an IBM 0.13μm CMOS process with a supply voltage of 2.5V. The maximum delay time skew resulting from simulation under various conditions is 4% and the clock circuit consumes 0.68 mW. Simulation results show that the clock generation circuit is suitable for high speed pipeline A / D converter.