An ultra-low specific on-resistance(Ron,sp) oxide trench-type silicon-on-insulator(SOI) lateral double-diffusion metal–oxide semiconductor(LDMOS) with an enhanced breakdown voltage(BV) is proposed and investigated by simulation. There are two key features in the proposed device: one is a U-shaped gate around the oxide trench, which extends from source to drain(UG LDMOS); the other is an N pillar and P pillar located in the trench sidewall. In the on-state, electrons accumulate along the U-shaped gate, providing a continuous low resistance current path from source to drain. The Ron,sp is thus greatly reduced and almost independent of the drift region doping concentration. In the off-state, the N and P pillars not only enhance the electric field(E-field) strength of the trench oxide, but also improve the E-field distribution in the drift region, leading to a significant improvement in the BV. The BV of 662 V and Ron,sp of 12.4 m?·cm2are achieved for the proposed UG LDMOS. The BV is increased by 88.6% and the Ron,sp is reduced by 96.4%, compared with those of the conventional trench LDMOS(CT LDMOS), realizing the state-of-the-art trade-off between BV and Ron,sp. An ultra-low specific on-resistance (Ron, sp) oxide trench-type silicon-on-insulator (SOI) lateral double-diffusion metal-oxide semiconductor (LDMOS) with an enhanced breakdown voltage (BV) is proposed and investigated by simulation There are two key features in the proposed device: one is a U-shaped gate around the oxide trench, which extends from source to drain (UG LDMOS); the other is an N pillar and P pillar is located in the trench sidewall. In the on-state, electron accumulate along the U-shaped gate, providing a continuous low resistance current path from source to drain. the N and P pillars not only enhance the electric field (E-field) strength of the trench oxide, but also improve the E-field distribution in the drift region, leading to a significant improvement in the BV. The BV of 662 V and Ron, sp of 12.4 m? Cm2are achieved for the proposed UG LDMOS. The BV is in creased by 88.6% and the Ron, sp is reduced by 96.4%, compared with those of the conventional trench LDMOS (CT LDMOS), realizing the state-of-the-art trade-off between BV and Ron, sp.