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随着数字信号处理技术的发展,FPGA正越来越频繁地用于实现基于高速硬件的高性能的科学计算.本文通过增加浮点加法器的流水线级数来提高其单位时间的吞吐量,探讨了充分利用FPGA内部丰富的触发器来提高系统主频的可行性.提出了一种指数和尾数操作、加法和减法操作均分离的多路径浮点加法器结构,对于单精度(32位)的操作数,采用Altera公司的StratixⅡ系列芯片,8级流水线可以达到356MHz以上的速度.
With the development of digital signal processing technology, FPGA is used more and more frequently to realize the high-performance scientific computing based on high-speed hardware.In this paper, we improve the throughput per unit time by increasing the pipeline stages of floating-point adder In order to make full use of the abundant triggers in the FPGA to improve the system frequency, a multi-path floating-point adder structure with exponential and mantissa operations and separate operations of addition and subtraction is proposed. For single-precision (32-bit) Operands, using Altera’s Stratix Ⅱ series of chips, 8-stage pipeline can reach more than 356MHz speed.